Bridge circuit for Ethernet powered device

ABSTRACT

A network powered device includes field effect transistors connected as bridge circuit. The bridge circuit includes control circuitry to enable the FETs based on completion of a powered device detection sequence performed by power sourcing equipment coupled to the device via an Ethernet link.

BACKGROUND

It is often convenient to position networked devices in locations thatlack access to an AC power outlet. To facilitate such positioning, powerover Ethernet (PoE) standards have been developed. PoE allows a powersourcing device, such as an Ethernet switch, to provide power to anetwork device via the data communication cabling (e.g., category 3cabling, category 5 cabling, etc.) that connects the network device andthe power sourcing device. IEEE 802.3af and IEEE 802.3at are examples ofPoE standards.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of examples of the invention, reference willnow be made to the accompanying drawings in which:

FIG. 1 shows a block diagram of a system employing power over Ethernet(PoE) in accordance with principles disclosed herein;

FIG. 2 shows a block diagram of a network device powered via PoE inaccordance with principles disclosed herein;

FIG. 3 shows a schematic diagram for an input bridge circuit used in anetwork device powered via PoE in accordance with principles disclosedherein; and

FIG. 4 shows a flow diagram for a method for using a field effecttransistor bridge in a network device powered via PoE in accordance withprinciples disclosed herein.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claimsto refer to particular system components. As one skilled in the art willappreciate, computer companies may refer to a component by differentnames. This document does not intend to distinguish between componentsthat differ in name but not function. In the following discussion and inthe claims, the terms “including” and “comprising” are used in anopen-ended fashion, and thus should be interpreted to mean “including,but not limited to . . . .” Also, the term “couple” or “couples” isintended to mean either an indirect or a direct connection. Thus, if afirst component couples to a second component, the connection may bethrough a direct connection or through an indirect connection via othercomponents and connections. The recitation “based on” is intended tomean “based at least in part on.” Therefore, if X is based on Y, X maybe based on Y and any number of other factors.

DETAILED DESCRIPTION

The following discussion is directed to various implementations of a FETbridge circuit used in a network device powered via Ethernet. Althoughone or more of these implementations may be preferred, theimplementations disclosed should not be interpreted, or otherwise used,as limiting the scope of the disclosure, including the claims. Inaddition, one skilled in the art will understand that the followingdescription has broad application, and the discussion of anyimplementation is illustrative and is not intended to intimate that thescope of the disclosure, including the claims, is limited to thatimplementation.

Power over Ethernet (PoE) can provide DC power to network-powereddevices over one of multiple sets of power conductors (e.g., two sets offour wires each) where each set of power conductors includes multiplepower conductors and multiple return conductors (e.g., a pair ofpositive wires and a pair of negative wires). While the polarity of thepower conductors is defined by the PoE standards, network-powereddevices should accommodate inadvertent reversals in power conductorpolarity. That is, the network-powered device must operate properlyregardless of the polarity of power received via the Ethernet cabling.The power input of a network powered device may include a bridge circuitto provide polarity insensitivity.

A bridge circuit for accommodating power polarity reversal typicallycomprises four diodes arranged as a diode bridge. The diodes provide therequisite polarity insensitivity, but the voltage drop across the diodesreduces power utilization efficiency of the network-powered device. Toimprove power utilization efficiency, a field effect transistor (FET)bridge may be employed rather than a diode bridge. Due to the lowresistance provided by the FET bridge, the voltage drop across the FETbridge may be substantially lower than that of a diode bridge.

While advantageously providing higher efficiency, application of FETbridges in PoE powered devices presents numerous issues anddifficulties. Power FETs are significantly more expensive than diodes,and a network-powered device includes two bridges to rectify the twosets of power conductors used by PoE, thereby further increasing thecost associated with using FET rather than diode bridges.

Use of FET bridges in a PoE powered device present additional problemswith regard to implementation in compliance with the requirements of thePoE standards (e.g., IEEE 802at-2009). The PoE standards do not appearto contemplate the use of FET bridges, and conventional FET bridgeimplementations can produce violations of the PoE standards that cause apowered device to fail PoE certification testing and/or fail to operateat all. The PoE powered device disclosed herein include bridges thatallow the PoE powered device to operate in compliance with PoE standardswhile providing the power efficiency characteristic of FET bridges.

FIG. 1 shows a block diagram of a system 100 employing power overEthernet (PoE) in accordance with principles disclosed herein. Thesystem 100 includes a powered device 102 and power sourcing equipment(PSE) 104 coupled via an Ethernet link 108. The PSE 104 may be a networkswitch, a hub, or any other equipment that provides power to the powereddevice 102 via the Ethernet link 108. The powered device 102 may be anydevice that receives power to operate via the Ethernet link 108. Forexample, the powered device 102 may be an internet protocol telephone, acamera, a computing device, a wireless access point, etc. The Ethernetlink 108 includes conductors for electrically transferring power, andoptionally data, between the PSE 104 and the powered device 102. TheEthernet link 108 may include category (Cat) 3 cable, Cat 5 cable, etc.

In order to determine whether a device to which the PSE 104 is connectedis to be powered via the Ethernet link 108, the PSE 104 executes apowered device detection sequence. During the detection sequence, thePSE 104 measures the resistance presented by the device 102 connected tothe PSE 104 via the Ethernet link 108. To measure the resistance, thePSE drives at least two different voltages onto the Ethernet link andmeasures the current flowing through the device 102 responsive to thevoltages. If the measured resistance is within a predetermined range,the PSE 104 determines that a powered device 102 is connected to theEthernet link 108 and proceeds to determine the power requirements ofand provide operating power to the powered device 102.

The powered device 102 includes FET bridges 106 at the power inputterminals connecting the powered device 102 to the Ethernet link 108.The FET bridges 106 reduce the voltage drop of the connection to theEthernet link 108, relative to diode bridges, thereby improving thepower efficiency of the powered device 102. Unfortunately, operation ofconventional FET bridges can interfere with the powered device detectionsequence by changing the resistance of the current path through thepowered device when the FETs are activated. Such changes in resistancemay cause the resistance measured by the PSE 104 to fall outside of theresistance range that identifies a powered device. Consequently,operation of the FET bridges may cause the PSE 104 to misidentify apowered device (i.e., a device to be powered via the Ethernet link 108)as a non-powered device. The FET bridges 106 include control circuitrythat prevents misidentification of the powered device 102 due to changesin resistance and prevents reverse voltage propagation through an unusedFET bridge.

FIG. 2 shows a block diagram of the network powered device 102 poweredvia PoE in accordance with principles disclosed herein. The PSE 104 mayprovide power to the powered device 102 via any one of multiple sets ofpower conductors of the Ethernet link 108. The FET bridges 106 includesmultiple instances of the FET bridge 202 (202-A/B) with one FET bridge202 coupled to each set of power conductors. The outputs of each FETbridge 202 are connected in parallel to provide power to the powersupply 204 that generates the various voltage levels that power thepowered device 102.

The bridges 202 are not isolated from one another using diodes becauseisolation diode voltage drops would negate the efficiency gains of theFET bridges 202. Because the outputs of the FET bridges 202 areconnected in parallel, the output of one bridge 202 may affect the otherbridge 202. For example, when bridge 202-A propagating power fromconductor set 1 to V_(DD) and V_(SS), the voltages on V_(DD) and V_(SS)are fed back into bridge 202-B and may affect the operation of bridge202-B. More specifically, the voltages on V_(DD) and V_(SS) may turn onthe FETs of the bridge 202-B. The FETs can conduct currentbidirectionally, consequently, when activated via the voltages on V_(DD)and V_(SS), the bridge 202-B may pass V_(DD) and V_(SS) voltages to theinputs of the bridge 202-B, and potentially onto conductor set 2 of theEthernet link 108. Presenting such voltage at a power input of thepowered device 102 is a violation of PoE standards and such devices maynot be certified for use in PoE systems. Each FET bridge 202 includescontrol circuitry that prevents an inactive FET bridge 202 from passingvoltage from V_(DD) and V_(SS) to the inputs of the inactive bridge 202.

FIG. 3 shows a schematic diagram for an input bridge circuit 202 used ina network device 102 powered via PoE in accordance with principlesdisclosed herein. The bridge 202 includes two P-channel metal oxidesemiconductor FETs (MOSFETs) Q1 and Q2, and two N-channel MOSFETs Q3 andQ4. The MOSFETs Q1, Q2, Q3, Q4 are connected to form a bridge. Thesource terminals of MOSFETs Q1 and Q2 are connected, and the sourceterminals of MOSFETs Q3 and Q4 are connected. The drain terminals ofMOSFETs Q1 and Q3 are connected to a first set of input terminals of thepowered device 102 for receiving power via a given conductor set theEthernet link 108. The drain terminals of MOSFETs Q2 and Q4 areconnected to a second set of input terminals of the powered device 102for receiving power via the given conductor set of the Ethernet link108.

MOSFETs Q1 and Q4 connect the input terminals of the powered device 102to the power supply 204 (i.e., bridge 202 input to bridge 202 output) ifline 302 is positive relative to line 304. MOSFETs Q2 and Q3 connect theinput terminals of the powered device 102 to the power supply 204 ifline 304 is positive relative to line 302.

The FET bridge 202 includes control circuitry that manages the operationof the MOSFETs Q1, Q2, Q3, and Q4. The voltage at the gate terminal ofMOSFET Q1 is controlled by resistors R1 and R2, transistor Q5, diodes D1and D5, and capacitor C1. Resistors R1 and R2 form a voltage dividerthat reduces the voltage at the gate of MOSFET Q1. MOSFET Q2 iscontrolled by resistors R3 and R4, transistor Q6, diodes D2 and D6, andcapacitor C2. MOSFET Q3 is controlled by resistors R5 and R6, transistorQ7, and diodes D3 and D7. MOSFET Q4 is controlled by resistors R7 andR8, transistor Q8, and diodes D4 and D8.

When the PSE 104 drives a voltage onto the Ethernet link 108, such thatthe voltage on line 302 of the FET bridge 202 is positive relative toline 304, when the voltage exceeds a diode forward voltage and theMOSFETs Q1 and Q4 are off, current flows through the FET bridge 202 viathe drain-source body diodes of the MOSFETs Q1 and Q4. Under suchconditions, the FET bridge 202 is equivalent to and operates as a diodebridge. When the voltage across the lines 302, 304 exceeds the reversevoltage of the zener diodes D1 and D4, current flows through the zenerdiodes D1 and D4 and turns on bipolar transistors Q5 and Q8. In turn,transistors Q5 and Q8 drive the gates of MOSFETs Q1 and Q4 and turn onthe MOSFETs Q1 and Q4 providing a low resistance connection of lines 302and 304 to V_(DD) and V_(SS) respectively. Similarly, when the voltageon line 304 of the FET bridge 202 is positive relative to line 302,MOSFETs Q2 and Q3, and associated circuitry, operate in accordance withthe description above to connect line 304 and 302 to V_(DD) and V_(SS)respectively.

Prior to providing operating power via the Ethernet link 108, the PSE104 executes a detection sequence to determine whether the device 102 isto be powered via the Ethernet link 108. The detection sequencedetermines a resistance of the device 102, where the resistance (e.g.,19-26 kilo-ohms) signifies whether the device 102 is to be powered viathe Ethernet link 108. The resistance of the device 102 is determined bymeasuring the current flowing through the device 102 at two differentdetection voltages provided to the device 102 by the PSE 104 via theEthernet link 108. For example, the PSE 104 may provide a firstdetection voltage (e.g., 4 volts) into the FET bridge 202 via theEthernet link 108 and measure the current flow, and thereafter provide asecond detection voltage (e.g., 8 volts) into the FET bridge 202 via theEthernet link 108 and measure the current flow. In some implementations,the first and second detection voltage may be any voltage between 2.8volts and 10 volts with at least one volt differential between the twodetection voltages. The PSE 104 may compute the resistance as:

$R = \frac{\left( {V_{2} - V_{1}} \right)}{\left( {I_{2} - I_{1}} \right)}$

The circuitry controlling activation of the MOSFETs Q1-Q4 ensures thatthe MOSFETs Q1-Q4 remain inactive during the detection sequence. Keepingthe MOSFETs Q1-Q4 off during the detection sequence is important becauseactivation of the MOSFETs Q1-Q4 during the detection sequence can changethe apparent resistance of the device 102 and erroneously indicate tothe PSE 104 that the device 102 is not to be powered via the Ethernetlink 108. For example, using the 4 volt and 8 volt detection voltagesreferred to above, if the 4 volt detection measurement is made withMOSFETs Q1 and Q4 off, and the 8 volt detection measurement is made withthe MOSFETs Q1 and Q4 on, the lower circuit resistance of the secondmeasurement may corrupt the overall resistance measurement.

The voltage level (i.e., across lines 302, 304) at which the MOSFETsQ1-Q4 turn on is controlled by the zener diodes D1-D4. In the FET bridge202, the zener diodes D1-D4 allow the MOSFETS Q1-Q4 to turn on onlyafter the detection sequence is complete. Consequently, the FET bridge202 operates as a diode bridge and presents a consistent resistancethroughout the detection sequence. The bridge resistance is lowered byactivating the MOSFETs only after the detection sequence is complete.Thus, after the detection sequence is complete, and the PSE 104increases the voltage on the lines 302-304 to a voltage that exceeds apredetermined detection voltage range and the zener diodes D1-D4activate the MOSFETs Q1-Q4. In some implementations, the zener diodesD1-D4 have a reverse voltage greater than 10 volts. In someimplementations, the zener diodes D1-D4 have a reverse voltage of 15volts. Using zener diodes D1-D4 having a reverse voltage of 15 volts,the MOSFETS Q1-Q4 are activated only after the voltage across lines302-304 exceeds 15 volts (i.e., after the detection sequence iscomplete). In a FET bridge implementation using a lower zener reversevoltage (e.g., 5 volts), or otherwise activating the FETs during thedetection sequence, the resistance measurement may be corrupted as thebridge resistance changes with FET activation.

The MOSFET control circuitry also prevents reverse voltage propagationthrough the FET bridges 202. As shown in FIG. 2, implementations of thepowered device 102 include at least two FET bridges 202-A, 202-B. Whichone of the two FET bridges 202 is activated to transfer power from theEthernet link 108 is determined based on which conductor set of theEthernet link 108 is selected for detection and power transfer by thePSE 104. Thus, if conductor set 1 is selected for power transfer, thenbridge 202-A is activated and bridge 202-B remains inactive. Similarly,if conductor set 2 is selected for power transfer, then bridge 202-B isactivated and bridge 202-A remains inactive. If a bridge 202 that shouldbe inactive is activated, the voltage from V_(DD) and V_(SS) willpropagate onto the conductors (or input terminals) connected to thebridge 202 in violation of the PoE standards. Such undesired activationmay occur if the MOSFETs Q1-Q4 are momentarily activated due to atransient voltage that creates a gate-source voltage differential at theMOSFETs Q1-Q4. The transient briefly turns on the MOSFETs Q1-Q4 and thevoltage propagated from V_(DD) and V_(SS) to lines 302-304 latches theMOSFETs Q1-Q4 on through the transistors Q5-Q8 and associatedcomponents.

The FET bridge 202 includes capacitors C1, C2 across the gate pull-upresistors R1, R3 of the P-channel MOSFETs Q1, Q2. The capacitors C1, C2provide filtering that reduces the effects of transients and transitionson the gate-source voltages of the MOSFETs Q1 and Q2. By reducing thegate-source voltage difference due to transients and transitions onV_(DD) and V_(SS), the capacitors C1, C2 prevent the MOSFETs Q1 and Q2from turning on, and producing reverse voltage, when the bridge 202 isnot being used to transfer power from the Ethernet link 108. Thus, theFET bridge 202 avoids the reverse voltage propagation occurring in FETbridges lacking such filtering.

FIG. 4 shows a flow diagram for a method for using a FET bridge in anetwork device powered via PoE in accordance with principles disclosedherein. Though depicted sequentially as a matter of convenience, atleast some of the actions shown can be performed in a different orderand/or performed in parallel. Additionally, some implementations mayperform only some of the actions shown.

In block 402, the PSE 104 is determining whether the device 102 is to bepowered via the Ethernet link 108. The PSE 104 executes a detectionsequence that drives at least two different voltages onto the Ethernetlink 108. The control circuitry of the FET bridge 202 disables theMOSFETs Q1-Q4 throughout the detection sequence and, throughout thedetection sequence, operates the FET bridge as a diode bridge.

In block 404, the detection sequence is complete and the PSE 104 raisesthe voltage provided to the device 102 to a voltage higher than isspecified in the PoE standards for use during the detection sequence. Inresponse to the non-detection voltage, the control circuitry of the FETbridge 202 activates the MOSFETs and reduces the resistance of the FETbridge 202.

In block 406, the control circuitry of the FET bridge (e.g., 202-B) thatis not connected to the conductor set of the Ethernet link 108 beingused for detection and power provision holds the MOSFETs of the FETbridge 202-B inactive by filtering transients and transitions on thepower supply voltages (V_(DD) and V_(SS)) driven by the active FETbridge 202-A. Holding the MOSFETs off prevents reverse voltage feedbackthrough the unused FET bridge 202-B.

Thus, the FET bridge 202 provides high efficiency in PoE applicationswhile avoiding problems and PoE standard violations that would occurwhen conventional FET bridges are applied in PoE applications. The PoEstandards fail to consider the difficulties of utilizing a FET bridge ina powered device. The operational issues addressed by the FET bridge 202are unknown in the prior art and the root causes are exceedinglydifficult to identify when encountered because while a conventional FETbridge will itself operate as expected, its operation raises issues inthe context of PoE that one skilled in art would not expect toencounter.

The above discussion is meant to be illustrative of the principles andvarious implementations of the present disclosure. Numerous variationsand modifications will become apparent to those skilled in the art oncethe above disclosure is fully appreciated. It is intended that thefollowing claims be interpreted to embrace all such variations andmodifications.

What is claimed is:
 1. A system, comprising: a network powered device tobe powered via conductors of an Ethernet link, the network powereddevice comprising: a plurality of bridge networks, each of the bridgenetworks to be coupled to power conductors of the Ethernet link andcomprising: a plurality of field effect transistors (FETs) connected asa bridge circuit; and a plurality of bipolar transistors, wherein, foreach FET of the plurality of FETs, a gate of the FET is coupled to acollector terminal of a unique one of the plurality of bipolartransistors, wherein the plurality of FETs are to pass current inresponse to a completion of a powered device detection sequenceperformed by power sourcing equipment coupled to the device via theEthernet link, and wherein, for each FET of the plurality of FETs, thegate is also coupled to a capacitor in parallel with a pull-up resistor.2. The system of claim 1, wherein each of the bridge networks furthercomprises a plurality of zener diodes, each of the zener diodes coupledto a base terminal of one the plurality of bipolar transistors; whereineach of the zener diodes comprises a reverse breakdown voltage that isgreater than the highest voltage provided by the power sourcingequipment via the Ethernet link as part of the detection sequence. 3.The system of claim 2, wherein each of the plurality of zener diodes hasa reverse breakdown voltage of at least eleven volts.
 4. The system ofclaim 1, wherein the bridge network is to operate as a diode bridgeuntil after completion of the detection sequence.
 5. The system of claim2, further comprising, for each bipolar transistor, a diode connectingthe base terminal of the bipolar transistor to one of the zener diodes.6. A network device, comprising: first terminals for receiving power viaan Ethernet link; a first bridge circuit coupled to the first terminalsand comprising: a pair of N-channel field effect transistors (FETs)coupled source to source; a pair of P-channel FETs coupled source tosource; a plurality of bipolar transistors; and a plurality of zenerdiodes, wherein, for each FET, a gate is coupled to a collector terminalof a bipolar transistor, and the gate is also coupled to a capacitor inparallel with a pull-up resistor, wherein each of the zener diodes iscoupled to a base terminal of one of the bipolar transistors, andwherein each of the zener diodes has a reverse breakdown voltage greaterthan the maximum voltage applied by power sourcing equipment todetermine whether the network device is to receive power via theEthernet link.
 7. The network device of claim 6, wherein the zenerdiodes have reverse breakdown voltage of at least eleven volts.
 8. Thenetwork device of claim 6, wherein the zener diodes have reversebreakdown voltage between fourteen and sixteen volts.
 9. The networkdevice of claim 6, wherein, for each bipolar transistor, an emitterterminal is coupled to one of the first terminals.
 10. The networkdevice of claim 6, further comprising, for each bipolar transistor, adiode connecting the base terminal to one of the zener diodes.
 11. Apower over Ethernet device, comprising: a plurality of bridge circuits,each of the bridge circuits comprising: inputs to be coupled to a set ofconductors of an Ethernet link; a plurality of field effect transistors(FETs); and a plurality of bipolar transistors, wherein, for each FET, agate of the FET is coupled to: a collector terminal of one of theplurality of bipolar transistors; and a capacitor in parallel with apull-up resistor, wherein the plurality of FETs are to pass currentbetween the inputs and outputs of the bridge circuit in response to acompletion of a powered device detection sequence performed by powersourcing equipment coupled to the device via the Ethernet link.
 12. Thepower over Ethernet device of claim 11, wherein each of the bridgecircuits further comprises a plurality of zener diodes, each of thezener diodes coupled to a base terminal of one the plurality of bipolartransistors, each of the zener diodes having a reverse breakdown voltagegreater than the predetermined maximum detection voltage.
 13. The powerover Ethernet device of claim 12, wherein each of the plurality of zenerdiodes has a reverse breakdown voltage of at least eleven volts.
 14. Thepower over Ethernet device of claim 11, wherein each of the bridgecircuits is to prevent current flow through the FETs between the inputsand outputs of one of the bridges that is not providing power to thedevice based on the other of the bridges providing power to the device.15. The power over Ethernet device of claim 12, further comprising, foreach bipolar transistor, a diode connecting the base terminal of thebipolar transistor to one of the zener diodes.
 16. The power overEthernet device of claim 11, wherein, in each bridge circuit, theplurality of FETs are disabled from passing current between the inputsand outputs of the bridge circuit during the powered device detectionsequence.
 17. The system of claim 1, wherein, in each bridge network,the plurality of FETs are disabled from passing any current during thepowered device detection sequence.
 18. The network device of claim 6,wherein the first bridge circuit prevents current flow through the FETsduring a powered device detection sequence performed by the powersourcing equipment.